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Missed this mention earlier but IC design insiders reveal that OSAT providers have already warned clients: "traditional packaging capacity could face a deficit exceeding 20% by 2027" (eg. $AMKR, ethereum:0x041ff0e49f6f774e7dc7bd10ee4a14c00b1d80b2, Powertech as potential beneficaries) With: "wire bonding equipment" emerging as the primary bottleneck (ASMPT, $KLIC) -> influx of AI server shipments has triggered a spike in demand for mature chips -> existing mature packaging capacity at OSATs is being rapidly absorbed -> securing early access to traditional packaging capacity is now becoming a challenge Cascading bottleneck patterns are occurring across memory (eg. DDR2, DDR3) and now packaging capacity I guess.