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SRAM scaling from N5 to N3E to N2 to A16 is very complicated. Headline bitcell size itself doesn't shrink much, but periphery seems to scale a lot through different DTCO. I'm trying to wrap my head around the methods of how/why Anyone of my followers wanna chat or DM about it? https://t.co/8la5GQ4GWR @Darth_Goldsmith ?