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Wonder what 2.5D advanced packaging / CoWoS looks like? ASE showed off a super cool model in Taiwan that demonstrates the various components of an advanced package "XPU / GPU" and how it is bound together by CoWoS (Chip on wafer on substrate) Center piece is the XPU logic die which does the calculations - (largest volumes made by $NVDA and $AVGO) The piece surrounding it with many layers is HBM - high bandwidth memory (made by SK Hynix, $MU, and Samsung) They are packaged together with microbumps onto the copper colored RDL. Underneath, silver colored is the silicon interposer. Finally they are placed onto the substrate itself. This complex process of advanced packaging is done to create a combined chip that is able to access different capabilities at a very fast rate (in the case of the XPU, it's to access the high bandwidth memory faster). Note you can see that the shoreline of the XPU (aka closest to the logic die for fastest I/O) is dominated by HBM. Often times AI workloads are memory bandwidth constrained, aka the constraint on the system is how fast the XPU can read and write their calculations to memory Advanced packaging is here to stay and continue to grow as techniques will expand past just the leading edge AI accelerators like GPUs and XPUs. In fact, $TSM on their last earnings call doubled their view of their Foundry TAM from $115B to $250B when including packaging, testing, and mass making! TSMC, ASE, Amkor are the leaders today in advanced packaging. In fact, ASE who presented this model invented this 2.5D - what TSMC calls CoWoS in 2014 alongside AMD. Fascinating times for the semis industry

_clarktang ↗